Implementation of Metal ECO using Mask Programmable Cell for Hold Timing Violations

Abstract

Day by day, technology continues to shrink while the transistor counts on chip increases, leading to greater design complexity. As a result, Metal ECO plays an important role in addressing last-minute changes and fixing violations in a cost-effective manner, saving both time and effort. In this article, we focus on Metal ECO implementation using mask-programmable cells (ECO filler cell) to fix hold timing violations.

After reading this article you will be able to answer the following questions: What is Metal ECO? Why is the Metal ECO stage important in the design cycle? What are different approaches used to fix hold at the Metal ECO stage? What is a mask-programmable cell? We will also go through an in-depth understanding of the methodology and implementation flow to fix hold violations using mask-programmable cells at the ECO stage and its advantages and disadvantages.

Introduction

What is Metal ECO?

Metal ECO is a process carried out by changing the Metal connection (Metal layers) only. This is a very common approach in the semiconductor industry and helps avoid a complete re-spin of silicon.

Advantages of Metal ECO:

1. Faster time-to-market
2. Cost-efficient solution

Overview and Approaches to Fix Hold Timing Violations with Metal ECO

Basic approaches to perform Metal ECO for hold fixes after the base tape-out is completed:

1. Net Detouring: This is a very basic and easy approach to fix hold timing violations. We select the appropriate nets and reroute them using detouring that adds delay and helps fix hold timing violation.

   Limitation:

   • If we have a high hold timing magnitude that requires more net detouring, it can cause transition failure.

2. Using Spare Cells: We can utilize spare cells that are already added to the design at the initial stage to fix hold timing violations. A spare cell includes a wide range of functional cells, both combinational and sequential. A spare cell module typically includes INV, BUF, FF, NAND, and NOR, and these are placed at regular intervals throughout the design. The input pins of these cells are tied off to avoid violating the floating input rule.

   Limitations:

   • Spare cells have limited drive strength of cells available in modules that can lead to other violations.
   • Sometimes the placement of spare cells is not at the required location.

3. Reutilizing Existing Buffer: We can reutilize the existing buffer for delay addition to fix hold timing violations. For that, you need to get an appropriate buffer with enough timing margin.

   Limitation:

   • To get a buffer with an appropriate timing margin at the required locations.

To overcome all the above issues and limitations, we have come up with a technique called the mask-programmable cell (ECO filler cell) approach.

Metal ECO Mask-Programmable Cell Approach

What is a Mask-Programmable Cell?

These are pre-designed cells developed in such a way that their functionality can be modified by changing only the Metal and via layers, while keeping the base layer footprint the same.

This approach addresses all the major issues and limitations of the above three methods. The usage of this approach is supported by mostly all the Electronic Design Automation (EDA) tools and library vendors in the semiconductor industry.

Note: The figure above is for reference, showing the same FEOL footprint, having only contact layers differences between the ECO filler cell and the ECO functional cell.

Methodology and Implementation Flow

1. Mapping Cell Information: The library vendor provides mapping cell information for filler/decap cells that can be replaced with functional cells. The table below shows examples of mapping information.
2. Getting VT, Orientation, and Location: We must get VT, orientation, and location information of the filler/decap cells that need to be replaced with functional cells. The newly added functional cells must maintain the same orientation and location to avoid base layer violations.

   After getting the orientation and location information of the filler/decap cells to be replaced, we can simply delete them.

   Command used: delete_inst

3. New Functional Cell Addition: Next, we need to add the mapped function cells (INV/BUF) with the same VT, orientation, and location to get base layer consistency without base violations. After that, check the empty space in the design and add non-Metal filler cells if there are gaps.

   Command used: eco_add_repeater -pins -name -cells -location

4. Power-ground (PG) Connect and Route: Once everything meets expectations, perform the global PG connect for the newly added cells and complete net routing for these cells. Command used: route_eco –target
5. Run Physical Verification (PV) and Static Timing Analysis (STA): After implementation, run STA and PV to ensure the violations are fixed with no new violations.

To verify the correctness of the entire process after implementation, we must run a Layout vs. Layout (LVL) check to ensure the design changes are correct.

The figure below shows the implementation of mask-programmable ECO in real design.

Before ECO After ECO

The above example shows how cell placement looks before and after ECO implementation using ECO cells.

• Here – HDBULTLL06_DCAP_CAQY2ECO_8 cells removed and added 2 HDBULTLL06_BUF_CAQECO_4 buffers.
• The remaining gaps were filled in with 2 HDBULTLL06_FILL_ECO_2 cells.

Hold timing comparisons before and after ECO implementation using ECO cells.

Advantages:

1. Reduced Design Turnaround Time: Last-minute changes can be easily implemented by reutilizing these cells, reducing the re-spin design time and efforts.
2. Cost Effective: Since the base/FEOL mask remains unchanged, metal ECO proves to be highly cost-effective.
3. Flexible and Easy Implementation: The required functional cells can be recreated or derived easily from a single filler cell, simplifying the process.

Disadvantages:

1. Extra layer mask cost.

We can also fix setup timing violations, design rule violations (such as transition and capacitance) in addition to fixing hold timing violations using mask-programmable cells. However, this article is focused on how to fix hold timing violations.

Conclusion

This article gives a detailed understanding of Metal ECO implementation using mask-programmable cells which is easy, efficient, and better than any other approach to fix hold timing violations once the base (FEOL) tape-out is completed. It covers details of each possible approach used to fix hold timing violations along with in-depth explanation of mask-programmable cells methodology, with their advantages and disadvantages. We have also provided a comparison of hold timing before and after ECO implementation.

About the Authors

Dhanyakumar Shahis working as a Physical Design Engineer with the position of Technical Lead at eInfochips – an Arrow company, in India. He holds a Bachelor of Engineering degree in Electronics and Communication from the A.D Patel Institute of Technology (ADIT), Vallabh Vidyanagar, Anand, India. With over eight years of hands-on experience in lower technology nodes (28nm, 16nm, 7nm, 5nm, 3nm) in ASIC design, he is an expert in Synthesis, Place and Route (PnR), Static Timing Analysis (STA) Analysis, Physical Verification (PV), and Front-end Integration (FEINT) activities.

Dharmik Lakhani is a Physical Design Engineer, currently serving as a Technical Lead, at eInfochips Ltd., India. He holds a Bachelor of Engineering degree in Electronics from Birla Vishvakarma Mahavidyalaya Engineering College (BVM), Vallabh Vidyanagar, Anand. With over eight years of hands-on experience in advanced ASIC design across leading-edge nodes such as 3nm, 5nm, 7nm, and 16nm, Dharmik has developed deep expertise in RTL-to-GDSII implementation. His core competencies include Synthesis, Place and Route (PnR), Static Timing Analysis (STA), Physical Verification, and Metal ECO execution. He has played a key role in multiple successful tape-outs, contributing to high-performance SoC designs with complex architectures and stringent timing requirements.